2 edition of Concurrent error-detecting codes for arithmetic processors found in the catalog.
Concurrent error-detecting codes for arithmetic processors
Raymond S Lim
by National Aeronautics and Space Administration, Scientific and Technical Information Branch, For sale by the National Technical Information Service] in Washington, D.C, [Springfield, Va
Written in English
|Statement||Raymond S. Lim|
|Series||NASA technical paper -- 1528|
|Contributions||United States. National Aeronautics and Space Administration. Scientific and Technical Information Branch, Ames Research Center|
|The Physical Object|
|Pagination||iii, 24 p. :|
|Number of Pages||24|
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Facts Concerning (4-bit) Two's Complement Arithmetic. Remark This is one place were the our treatment must go a little out of order. Appendix B in the book assumes you have read the chapter on computer arithmetic; in particular it assumes that you know about two's complement arithmetic. This demands concurrent, periodical, or on-demand monitoring and testing of the hardware structures to detect and classify deviations from the nominal behavior and appropriate reactions. This survey discusses suitable self-test, self-checking, and self-diagnosis methods for the realization of self-awareness and presents two case studies in.
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Concurrent error-detecting codes for arithmetic processors. Washington, D.C.: National Aeronautics and Space Administration, Scientific and Technical Information Branch ; [Springfield, Va.: For sale by the National Technical Information Service], (OCoLC) Material Type: Government publication, National government publication.
Digital Electronics and Design with VHDL offers a friendly presentation of the fundamental principles and practices of modern digital design. Unlike any other book in this field, transistor-level implementations are also included, which allow the readers to gain a solid understanding of a circuit's real potential and limitations, and to develop a realistic perspective on the practical design.
In our secure architectures, several computing types of systolic array structures are adopted to implement the MFMs, and two error-detecting styles based on linear arithmetic codes are employed to. Concurrent error-detecting codes for arithmetic processors / (Washington, D.C.: National Aeronautics and Space Administration, Scientific and Technical Information Branch ; [Springfield, Va.: For sale by the National Technical Information Service], ), by Raymond S.
As a consequence of studies concerning a fault-tolerant microprogrammed microprocessor an error-detection and error-correction scheme for logical operations has been developed. Implementing inverse Cited by: 1. primitives of the arithmetic adders, the main block design of a totally self-checking n-bit arithmetic adder based on two Concurrent error-detecting codes for arithmetic processors book encoding can be presented as below [Fig.
Fig. 3 Self-Checking Arithmetic Adders design The sum/carry/propagate bits which are prior of a particular adder are two-rail encoded byFile Size: 2MB. A novel approach to designing concurrent-error-detecting arithmetic and logic units using Berger code is presented.
Several theorems are developed on Berger check predictions for arithmetic and. The nonlinear SEC-DED codes are generalized from the existing perfect nonlinear codes (Vasil’ev codes, Probl Kibern –, ; Phelps codes, SIAM J Algebr Discrete Methods –, ; and the codes based on one switching constructions, Etzion and Vardy, IEEE Trans Inf Theory –, ).Cited by: detecting and correcting errors in sectors of data read from said disk by consecutively performing a sequence of processing steps chosen in accordance with said Reed-Solomon decoding principles, wherein each step is performed by a separate processor, and wherein these processors perform said steps in a pipelined manner with respect to sequentially read sectors and at a rate which provides Cited by: The aims of this book are twofold.
First, it attempts to bring together in a unified manner some of the recent research results on the use of error-detecting and error-correcting codes in computer systems design. Second, it serves as a self-contained text for advanced.
CADAC: A Controlled-Precision Decimal Arithmetic Unit. Finite Precision Rational Arithmetic: Slash Number Systems. Finite Precision Lexicographic Continued Fraction Number Systems. An Overflow/Underflow-Free Floating-Point Representation of Numbers. A Closed Computer Arithmetic. Part VII: IMPLEMENTATIONS.
Editor's Comments on Papers 38 Through This banner text can have markup. web; books; video; audio; software; images; Toggle navigation. Behrooz Parhami: 7/06/19 || E-mail: [email protected] || Problems: [email protected] Other contact info at: Bottom of this page || Go up to: B.
Parhami's. Two different solutions were presented by Tamir and Tremblay () for microrollback in a single-state register: the FIFO and RAM methods.
The FIFO solution is shown in Figure The storage data structure is a FIFO that contains all previous values of the register with associated valid bits up to N clock cycles. The current register is the register at the top of the FIFO structure and.
Error-Detecting Codes. This section illustrates the use of error-detecting codes (EDCs) for detecting faults in the encryption process of symmetric key ciphers. Similar rules apply to using EDCs during the decryption and key schedule procedures, because these use the.
Citation data can also be found on his Google Scholar profile, which, as of Septemlists total citations (, since ), an h-index of 32 (17, since ), citations of his book on computer arithmetic , and // citations for his three most cited papers //.
There are + citations to. This is the new edition of the classic book Computer Arithmetic in three volumes published originally in by IEEE Computer Society Press. As in the original, the book contains many classic papers treating advanced concepts in computer arithmetic, which is very suitable as stand-alone textbooks or complementary materials to textbooks on.
While Moore’s law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays.
These exaggerated delays widen the gap between the average and the worst case behavior of a by: A second course in computing with an emphasis on modern software development and principles central to computer science. Topics include software requirements, testing, object-oriented design, abstraction, encapsulation, recursion, and time-complexity.
Prerequisite:. J-Y. Jou and J.A. Abraham, “Fault-Tolerant Matrix Arithmetic and Signal Processing on Highly Concurrent Computing Structures,” Proceedings of the IEEE, Vol Number 5, Cited by: 1. Full text of "Reliable computer systems: design and evaluation" See other formats.Full text of "Computer Arithmetic Algorithms And Hardware Designs 2nd Edition" See other formats.“Concurrent Delay Testing in Totally Self-Checking Systems”, A.
Paschalis, D. Gizopoulos and N. Gaitanis. Book series: Frontiers in Electronic Testing, Volume On-Line Testing for VLSI, ChapterKluwer Academic Publishers,(selected set of articles).